H8SXSLASH1663M datasheet(582/1504 Pages) RENESAS

582 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 550 of 1468

REJ09B0412-0200

(6)

Transfer End by NMI Interrupt

If an NMI interrupt occurs, the EXDMAC clears the DTE bit to 0 in all channels and sets the

ERRF bit in EDMDR_0 to 1. EXDMA transfer is aborted when an NMI interrupt is generated

during EXDMA transfer. To perform EXDMA transfer after an NMI interrupt occurs, clear the

ERRF bit to 0 and then set the DTE bit to 1 in all channels.

The following explains the transfer end timing in each mode after an NMI interrupt is detected.

(a)

Normal transfer mode and repeat transfer mode

In dual address mode, EXDMA transfer ends at the end of the EXDMA transfer write cycle in

units of transfers.

In single address mode, EXDMA transfer ends at the end of the EXDMA transfer bus cycle in

units of transfers.

(b)

Block transfer mode

A block size EXDMA transfer is aborted. A block size transfer is not correctly executed, thus

matching between the actual transfer and the transfer request is not guaranteed.

In dual address mode, a write cycle corresponding to a read cycle is executed as well as in the

normal transfer mode.

(c)

Cluster transfer mode

A cluster size EXDMA transfer is aborted. If transfer is aborted in a read cycle, the read data is not

guaranteed. If transfer is aborted in a write cycle, the data not transferred is not guaranteed.

Matching between the transfer counter and the address register is not guaranteed since the transfer

processing cannot be controlled.

(7)

Transfer End by Address Error

If an address error occurs, the EXDMAC clears the DTE bit to 0 in all channels, and set the ERRF

bit in EDMDR_0 to 1. An address error during EXDMA transfer forcibly terminates the transfer.

To perform EXDMA transfer after an address error occurs, clear the ERRF bit to 0 and then set

the DTE bit to 1 in each channel.

The transfer end timing after address error detection is the same as for the one when an NMI

interrupt occurs.

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