H8SXSLASH1663M datasheet(587/1504 Pages) RENESAS

587 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 555 of 1468

REJ09B0412-0200

TSEIE bit

Activation source occurred

in the transfer size error state

RPTIE bit

Activation source occurred

after BKSZ changed from 1 to 0

SARIE bit

Source address extended

repeat area overflow occurred

DARIE bit

Destination address extended

repeat area overflow occurred

DTIE bit

DTIF bit

Transfer

end interrupt

Condition to set DTIF bit to 1: DTCR

is set to 0 and transfer ends.

ESIE bit

ESIF bit

Condition to set ESIF bit to 1

Transfer escape

end interrupt

Figure 11.70 Interrupts and Interrupt Sources

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Transfer end interrupt of

exception handling routine

Transfer continuation processing

Change register settings

Write 1 to DTE bit

End of interrupt handling routine

(RTE instruction execution)

End of transfer restart processing

Transfer restart after end of

interrupt handling routine

Clear DTIF or ESIF bit to 0

End of interrupt handling routine

[1] Write set values to the registers

(transfer counter, address registers, etc.)

[2] Write 1 to the DTE bit in EDMDR to restart

EXDMA operation. When 1 is written to

the DTE bit, the DTIF or ESIF bit in EDMDR is

automatically cleared to 0 and the interrupt

source is cleared.

[3] The interrupt handling routine is

ended with an RTE instruction, etc.

[4] Write 0 to the DTIF or ESIF bit

in EDMDR by first reading 1 from it.

[5] After the interrupt handling routine is

ended with an RTE instruction, etc.,

interrupt masking is cleared.

[6] Write set values to the registers

(transfer counter, address registers, etc.).

[7] Write 1 to the DTE bit in EDMDR

to restart EXDMA operation.

Change register settings

Write 1 to DTE bit

End of transfer restart processing

Figure 11.71 Procedure for Clearing Transfer End Interrupt and Restarting Transfer

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