H8SXSLASH1663M datasheet(592/1504 Pages) RENESAS

592 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 560 of 1468

REJ09B0412-0200

Figure 12.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to

the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus

connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC

transfer information.

Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR

must be set to 1.

DTCCR

Interrupt controller

Interrupt source clear

request

ACK

REQ

DTCVBR

DTC

CPU interrupt request

MRA

MRB

SAR

DAR

CRA

CRB

DTC activation request

vector number

MRA, MRB:

SAR:

DAR:

CRA, CRB:

DTCERA to DTCERF:

DTCCR:

DTCVBR:

DTC mode registers A, B

DTC source address register

DTC destination address register

DTC transfer count registers A, B

DTC enable registers A to F

DTC control register

DTC vector base register

DTCERA

DTCERF

External

memory

External device

(memory mapped)

Bus controller

Bus interface

control

Activation

control

Interrupt

control

On-chip

ROM

On-chip

ROM

On-chip

peripheral

module

[Legend]

Figure 12.1 Block Diagram of DTC

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