H8SXSLASH1663M datasheet(602/1504 Pages) RENESAS

602 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 570 of 1468

REJ09B0412-0200

Start

address

4 bytes

MRA

SAR

MRB

DAR

CRA

CRB

MRA

SAR

MRB

DAR

CRA

CRB

MRA MRB

Reserved

(0 write)

MRA MRB

Reserved

(0 write)

SAR

DAR

CRA

CRB

CRA

CRB

SAR

DAR

Transfer information

in short address mode

Chain

transfer

Transfer information

for one transfer

(3 longwords)

Transfer information

for the 2nd transfer

in chain transfer

(3 longwords)

Lower addresses

Transfer information

in full address mode

Transfer

information

for one transfer

(4 longwords)

Transfer

information

for the 2nd

transfer

in chain transfer

(4 longwords)

Start

address

4 bytes

Chain

transfer

Figure 12.2 Transfer Information on Data Area

Transfer information (1)

start address

Transfer information (2)

start address

Transfer information (n)

start address

Vector table

Upper: DTCVBR

Lower: H'400 + vector number

× 4

DTC vector

address

+4n

Transfer information (1)

4 bytes

Transfer information (2)

Transfer information (n)

Figure 12.3 Correspondence between DTC Vector Address and Transfer Information

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