H8SXSLASH1663M datasheet(619/1504 Pages) RENESAS

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Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 587 of 1468

REJ09B0412-0200

Table 12.10 Number of Cycles Required for Each Execution State

Object to be Accessed

On-Chip

RAM

On-Chip

ROM

On-Chip I/O

Registers

External Devices

Bus width

Access cycles

Vector read S

 



12 + 4m

6 + 2m

Transfer information read S

 



12 + 4m

6 + 2m

Execution

status

Transfer information write S

 



12 + 4m

6 + 2m

Byte data read S

3 + m

Word data read S

4 + 2m

3 + m

Longword data read S

12 + 4m

6 + 2m

Byte data write S

3 + m

Word data write S

4 + 2m

3 + m

Longword data write S

12 + 4m

6 + 2m

Internal operation S

[Legend]

m: Number of wait cycles 0 to 7 (For details, see section 9, Bus Controller (BSC).)

The number of execution cycles is calculated from the formula below. Note that

Σ means the sum

of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution cycles = I • S

I + Σ (J • SJ + K • SK + L • SL + M • SM) + N • SN

12.5.10

DTC Bus Release Timing

The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The

DTC releases the bus after a vector read, transfer information read, a single data transfer, or

transfer information writeback. The DTC does not release the bus during transfer information

read, single data transfer, or transfer information writeback.

12.5.11

DTC Priority Level Control to the CPU

The priority of the DTC activation sources over the CPU can be controlled by the CPU priority

level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits

DTCP2 to DTCP0. For details, see section 7, Interrupt Controller.

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