H8SXSLASH1663M datasheet(950/1504 Pages) RENESAS

950 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 918 of 1468

REJ09B0412-0200

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR

[2]

Write transmit data to TDR

and clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and

set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted?

TEND = 1

Break output

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin. After the TE bit is set to

1, a 1 is output for a frame, and

transmission is enabled.

[2] SCI state check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

read 1 from the TDRE flag to

confirm that writing is possible,

then write data to TDR, and clear

the TDRE flag to 0. However, the

TDRE flag is checked and cleared

automatically when the DMAC or

DTC is initiated by a transmit data

empty interrupt (TXI) request and

writes data to TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set DDR for the port

corresponding to the TxD pin to 1,

clear DR to 0, then clear the TE bit

in SCR to 0.

Figure 19.10 Example of Serial Transmission Flowchart

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