H8SXSLASH1663M datasheet(1009/1504 Pages) RENESAS

1009 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 977 of 1468

REJ09B0412-0200

20.3.8

Interrupt Enable Register 1 (IER1)

IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set

to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the

CPU. The interrupt vector number is determined by the contents of interrupt select register 1

(ISR1).

Bit

Bit Name

Initial Value

R/W



EP3 TR

R/W

EP3 TS

R/W

VBUSF

R/W

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

These bits are always read as 0. The write value

should always be 0.

EP3 TR

R/W

EP3 Transfer Request

EP3 TS

R/W

EP3 Transmission Complete

VBUSF

R/W

USB Bus Connect

20.3.9

Interrupt Enable Register 2 (IER2)

IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set

to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the

CPU. The interrupt vector number is determined by the contents of interrupt select register 2

(ISR2).

Bit

Bit Name

Initial Value

R/W

SSRSME

R/W



SURSE

R/W

CFDN

R/W



SETCE

R/W

SETIE

R/W

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