H8SXSLASH1663M datasheet(1021/1504 Pages) RENESAS

1021 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 989 of 1468

REJ09B0412-0200

20.3.22

Endpoint Stall Register (EPSTL)

The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set

to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0

is cleared automatically on reception of 8-byte command data for which decoding is performed by

the function and the EP0 STL bit is cleared. When the SETUPTS flag in the IFR0 register is set to

1, writing 1 to the EP0 STL bit is ignored. For detailed operation, see section 20.7, Stall

Operations.

Bit

Bit Name

Initial Value

R/W



EP3STL

R/W

EP2STL

R/W

EP1STL

R/W

EP0STL

R/W

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

These bits are always read as 0. The write value

should always be 0.

EP3STL

R/W

EP3 Stall

When this bit is set to 1, endpoint 3 is placed in the

stall state.

EP2STL

R/W

EP2 Stall

When this bit is set to 1, endpoint 2 is placed in the

stall state.

EP1STL

R/W

EP1 Stall

When this bit is set to 1, endpoint 1 is placed in the

stall state.

EP0STL

R/W

EP0 Stall

When this bit is set to 1, endpoint 0 is placed in the

stall state.

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