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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H8SX/1663M 데이터시트(PDF) 1165 Page - Renesas Technology Corp |
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H8SX/1663M 데이터시트(HTML) 1165 Page - Renesas Technology Corp |
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1165 / 1504 page  Section 25 Flash Memory Rev. 2.00 Sep. 24, 2008 Page 1133 of 1468 REJ09B0412-0200 Bit Bit Name Initial Value R/W Description 31 to 16 Unused These bits should be cleared to 0. 15 to 0 F15 to F0 R/W Frequency Set These bits set the operating frequency of the CPU. When the PLL multiplication function is used, set the multiplied frequency. The setting value must be calculated as follows: 1. The operating frequency shown in MHz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. The value multiplied by 100 is converted to the binary digit and is written to FPEFEQ (general register ER0). For example, when the operating frequency of the CPU is 35.000 MHz, the value is as follows: 1. The number of three decimal places of 35.000 is rounded. 2. The formula of 35.00 × 100 = 3500 is converted to the binary digit and B'0000 1101 1010 1100 (H'0DAC) is set to ER0. |
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