H8SXSLASH1663M datasheet(135/1504 Pages) RENESAS

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H8SX/1663M 데이터시트(PDF) 135 Page - Renesas Technology Corp

부품명	H8SX/1663M

상세설명	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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135 / 1504 page

Section 4 Resets

Rev. 2.00 Sep. 24, 2008 Page 103 of 1468

REJ09B0412-0200

4.7

Deep Software Standby Reset

This is an internal reset generated when deep software standby mode is canceled by an interrupt.

When deep software standby mode is canceled, a deep software standby reset is generated, and

simultaneously, clock oscillation starts. After the time specified with DPSWCR has elapsed, the

deep software standby reset is canceled.

For details of the deep software standby reset, see section 28, Power-Down Modes.

4.8

Watchdog Timer Reset

This is an internal reset generated by the watchdog timer.

When the RSTE bit in RSTCSR is set to 1, a watchdog timer reset is generated by a TCNT

overflow. After a certain time, the watchdog timer reset is canceled.

For details of the watchdog timer reset, see section 18, Watchdog Timer (WDT).

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