H8SXSLASH1663M datasheet(193/1504 Pages) RENESAS

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Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 161 of 1468

REJ09B0412-0200

7.6.4

Interrupt Response Times

Table 7.4 shows interrupt response times – the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The symbols for execution

states used in table 7.4 are explained in table 7.5.

This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in on-

chip ROM and the stack area in on-chip RAM enables high-speed processing.

Table 7.4

Interrupt Response Times

Normal Mode*

Advanced Mode

Maximum Mode*

Execution State

Interrupt

Control

Mode 0

Interrupt

Control

Mode 2

Interrupt

Control

Mode 0

Interrupt

Control

Mode 2

Interrupt

Control

Mode 0

Interrupt

Control

Mode 2

Interrupt priority determination*

Number of states until executing

instruction ends*

1 to 19 + 2·S

PC, CCR, EXR stacking

K to 2·SK*

2·S

K to 2·SK*

2·S

Vector fetch

Instruction fetch*

2·S

Internal processing*

Total (using on-chip memory)

10 to 31

11 to 31

10 to 31

11 to 31

Notes: 1. Two states for an internal interrupt.

2. In the case of the MULXS or DIVXS instruction

3. Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine.

4. Internal operation after interrupt acceptance or after vector fetch

5. Not available in this LSI.

6. When setting the SP value to 4n, the interrupt response time is S

K; when setting to 4n +

2, the interrupt response time is 2·S

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