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H8SX/1663M 데이터시트(PDF) 254 Page - Renesas Technology Corp

부품명 H8SX/1663M
상세설명  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
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H8SX/1663M 데이터시트(HTML) 254 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 222 of 1468
REJ09B0412-0200
For example, in an external address space access where the frequency rate of I
φ and Bφ is n : 1,
the operation is performed in synchronization with B
φ. In this case, external 2-state access space is
2n cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number
of access cycles is counted based on I
φ.
If the frequencies of I
φ, Pφ and Bφ are different, the start of bus cycle may not synchronize with
P
φ or Bφ according to the bus cycle initiation timing. In this case, clock synchronization cycle
(Tsy) is inserted at the beginning of each bus cycle.
For example, if an external address space access occurs when the frequency rate of I
φ and Bφ is
n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when
the frequency rate of I
φ and Pφ is m : 1, 0 to m-1 cycles of Tsy may be inserted.
Figure 9.6 shows the external 2-state access timing when the frequency rate of I
φ and Bφ is 4 : 1.
Figure 9.7 shows the external 3-state access timing when the frequency rate of I
φ and Bφ is 2 : 1.



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