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H8SX/1663M 데이터시트(PDF) 260 Page - Renesas Technology Corp |
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H8SX/1663M 데이터시트(HTML) 260 Page - Renesas Technology Corp |
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260 / 1504 page ![]() Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 228 of 1468 REJ09B0412-0200 Table 9.3 Pin Functions in Each Interface Pin Name B φ SDRAM φ CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 BS RD/ WR AS AH RD LHWR/LUB LLWR/LLB RAS CAS WE LUCAS/DQMLU LLCAS/DQMLL OE CKE WAIT 16 O O O O O O O O O O O 8 O O O O O O O O O O 16 O O O O O O O O O O O 8 O O O O O O O O O O 16 O O O O O O O O O O 16 O O O O O O O O O O O O O 8 O O O O O O O O O O O O 8 O O O O O O O O O 16 O O O O O O O O O O O O O O O O 16 O O O O O O O O O O O O O O O O 8 O O O O O O O O O O O O O O O 16 Output (Output) Output Output Output Output Output 8 Output (Output) Output Output Output Output Output Controlled by MD3 [Legend] O: Used as bus control signal. : Not used as bus control signal (I/O port as initial state). Initial State Basic Bus Byte-Control SRAM DRAM SDRAM Burst ROM Address/Data Multiplexed I/O Controlled by DRAME and OEE Controlled by WAITE Controlled by DRAME and OEE Remarks Single Chip |
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