M32CSLASH86 datasheet(341/505 Pages) RENESAS

341 / 505 page

Page 318

23. CAN Module

)

(

CANi Control Register 0 (i=0, 1)

Symbol

Address

After Reset(1)

C0CTLR0

020116 - 020016

XXXX 0000 XX01 0X012

C1CTLR0

028116 - 028016

XXXX 0000 XX01 0X012

RESET1

TSPRE0

TSRESET

CAN Reset Bit 1

Time Stamp

Counter Reset Bit

0: CAN module reset exited

1: CAN module is reset(2)

RESET0

LOOPBACK

(b2)

BASICCAN

CAN Reset Bit 0

Loop Back Mode

Select Bit

BasicCAN Mode

Select Bit

0: Disables BasicCAN mode function

1: Enables BasicCAN mode function

0: Disables loop back function

1: Enables loop back function

0: CAN module reset exited

1: CAN module is reset(2)

TSPRE1

ECRESET

(b15 - b12)

(b7 - b6)

(b5)

Error Counter

Reset Bit

0: Nothing is occurred

1: This bit is automatically set to "0" after

the CiTEC and CiREC registers are

set to "0016"(3)

Time Stamp

Prescaler Select Bit

Reserved Bit

Set to "0"

Bit Name

Function

Bit

Symbol

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

NOTES:

1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after

reset and supplying the clock to the CAN module.

2. Set the RESET1 and RESET0 bits to the same value simultaneously.

3. These bits can only be set to "1", not "0", by program.

0 0: Selects the CAN bus bit clock

0 1: Selects the CAN bus bit clock divided by 2

1 0: Selects the CAN bus bit clock divided by 3

1 1: Selects the CAN bus bit clock divided by 4

b9 b8

0: Nothing is occurred

1: This bit is automatically set to "0" after

the CiTSR register is set to "000016"(3)

b15

23.1 CAN-Associated Registers

Figures 23.3 to 23.18, and Figures 23.20 to 23.33 show registers associated with CAN. To access the

CAN-associated registers, set the CM21 bit in the CM2 register to "0" (main clock or PLL clock as CPU

clock) and the MCD4 to MCD0 bits in the MCD register to "100102" (no division mode). Or, set the PM24 bit

in the PM2 register to "1" (main clock direct mode) and the PM25 bit in the PM2 regiseter to "1" (CAN clock).

Two wait states are added into the bus cycle.

Refer to 7. Processor Mode and 9. Clock Generation Circuit.

23.1.1 CANi Control Register 0 (CiCTLR0 Register) (i=0, 1)

Figure 23.3 C0CTLR0 and C1CTLR0 Registers

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