M32CSLASH86 datasheet(367/505 Pages) RENESAS

367 / 505 page

Page 344

23. CAN Module

)

(

Figure 23.24 C0GMR2, C0LMAR2 and C0LMBR2 Registers

C1GMR2, C1LMAR2 and C1LMBR2 Registers

CANi Global Mask Register Extended ID0(1)

CANi Local Mask Register A Extended ID0(1)

CANi Local Mask Register B Extended ID0(1) (i=0, 1)

EID14M

EID15M

EID16M

EID17M

(b7 - b4)

Extended ID14

0: No ID is verified

1: ID is verified

Extended ID15

Extended ID16

Extended ID17

Bit Name

Function

Bit

Symbol

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

NOTES:

1. The CiGMR2, CiLMAR2 and CiLMBR2 registers can be accessed only when the BANKSEL bit in

the CiCTLR1 register is set to "1" (mask register selected).

2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after

reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".

3. The C0LMAR2 register shares the same address with the C0MCTL2 register.

4. The C1LMAR2 register shares the same address with the C1MCTL2 register.

5. The C0LMBR2 register shares the same address with the C0MCTL10 register.

6. The C1LMBR2 register shares the same address with the C1MCTL10 register.

Symbol

Address

After Reset(2)

C0GMR2, C1GMR2

022A16, 02AA16

XXXX 00002

C0LMAR2, C1LMAR2

023216(3), 02B216(4)

XXXX 00002

C0LMBR2, C1LMBR2

023A16(5), 02BA16(6)

XXXX 00002

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