 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
M32C/86 데이터시트(PDF) 436 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M32C/86 데이터시트(HTML) 436 Page - Renesas Technology Corp |
|
|
436 / 505 page  Page 413 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 25. Flash Memory Version ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Table 25.5 Status Register D0 to D7: These data buses are read when the read status register command is executed. NOTES: 1. The FMR07 (SR5) and FMR06 (SR4) bits are set to "0" by executing the clear status register command. When the FMR07 (SR5) or FMR06 (SR4) bit is set to "1", the program, block erase, erase all unlocked block and lock bit program commands are not accepted. Bits in SRD register SR4 (D4) SR5 (D5) SR7 (D7) SR6 (D6) Status Name Definition SR1 (D1) SR2 (D2) SR3 (D3) SR0 (D0) Program status Erase status Sequencer status Reserved bit Reserved bit Reserved bit Reserved bit "1" READY - - - - - "0" BUSY - - - - - Reserved bit Bits in FMR0 Register FMR00 FMR07 FMR06 Value after Reset 1 0 0 Successfully completed Successfully completed - - - - - Error Error (1) (1) |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
