M32CSLASH86 datasheet(484/505 Pages) RENESAS

484 / 505 page

Page 461

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27.7 Interrupts

27.7.1 ISP Setting

After reset, the ISP is set to "00000016". The program runs out of control if an interrupt is acknowledged

before the ISP is set. Therefore, the ISP must be set before an interrupt request is generated. Set the ISP

to an even address, which allows interrupt sequences to be executed at a higher speed.

_______

To use NMI interrupt, set the ISP at the beginning of the program. The NMI interrupt can be acknowl-

edged after the first instruction has been executed after reset.

_______

27.7.2 NMI Interrupt

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• NMI interrupt cannot be denied. Connect the NMI pin to VCC via a resistor (pull-up) when not in use.

_______

• The P8_5 bit in the P8 register indicates the NMI pin value. Read the P8_5 bit only to determine the pin

_______

level after a NMI interrupt occurs.

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• "H" and "L" signals applied to the NMI pin must be over 2 CPU clock cycles + 300 ns wide.

_______

• NMI interrupt request may not be acknowledged if this and other interrupt requests are generated

simultaneously.

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27.7.3 INT Interrupt

• Edge Sensitive

______

"H" and "L" signals applied to the INT0 to INT5 pins must be at least 250 ns wide, regardless of the CPU

clock.

• Level Sensitive

______

"H" and "L" signals applied to the INT0 to INT5 pins must be at least 1 CPU clock cycle + 200 ns wide.

For example, "H" and "L" must be at least 234ns wide if XIN=30MHz with no division.

______

• The IR bit setting may change to "1" (interrupt requested) when switching the polarity of the INT0 to INT5

pins. Set the IR bit to "0" (no interrupt requested) after selecting the polarity. Figure 27.3 shows an

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example of the switching procedure for the INT interrupt.

27. Precautions (Interrupts)

Set the POL bit in the INTiIC register

Set the IR bit in the INTiIC register to "0"

Set the ILVL2 to ILVL0 bits to "0012" (level 1)

to "1112" (level 7)

(INT interrupt request acknowledgement enabled)

Set the ILVL2 to ILVL0 bits in the INTiIC

(INT interrupt disabled)

______

Figure 27.3 Switching Procedure for INT Interrupt

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