| 전자부품 데이터시트 검색엔진 |
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M32C/86 데이터시트(PDF) 192 Page - Renesas Technology Corp |
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M32C/86 데이터시트(HTML) 192 Page - Renesas Technology Corp |
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192 / 505 page ![]() Page 169 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 15. Timer (Timer B) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M 15.2.3 Pulse Period/Pulse Width Measurement Mode In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. (See Table 15.11) Figure 15.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse width measurement mode. Figure 15.23 shows an operation example in pulse period measurement mode. Figure 15.24 shows an operation example in the pulse width measurement mode. Table 15.11 Pulse Period/Pulse Width Measurement Mode Specifications Item Specification Count Source f1, f8, f2n(3), fC32 Counting Operation • The timer increments a counter value Counter value is transferred to the reload register on the valid edge of a pulse to be measured. It is set to "000016" and the timer continues counting Counter Start Condition The TBiS bits (i=0 to 5) in the TABSR and TBSR register are set to "1" (starts counting) Counter Stop Condition The TBiS bit is set to "0" (stops counting) Interrupt Request Generation Timing • On the valid edge of a pulse to be measured(1) • The timer counter overflows The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the TBiS bit is set to "1" (start counting) and the next count source is counted after setting the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to the TBiMR register. TBiIN Pin Function Input for a pulse to be measured Read from Timer The TBi register indicates reload register values (measurement results)(2) Write to Timer Value written to the TBi register can be written to neither reload register nor counter NOTES: 1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the timer has started counting. 2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid edge after the timer has started counting. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). |
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