M32CSLASH86 datasheet(210/505 Pages) RENESAS

210 / 505 page

Page 187

17. Serial I/O

)

(

UARTi Transmit/Receive Control Register 0 (i=0 to 4)

Symbol

Address

After Reset

U0C0 to U4C0

036C16, 02EC16, 033C16, 032C16, 02FC16

0000 10002

TXEPT

CRD

NCH

UFORM

CKPOL

CLK0

CRS

CLK1

UiBRG Count

Source Select Bit

CST/RTS Function

Select Bit

Transmit Register

Empty Flag

CTS/RTS Disable

Bit

Data Output Select

Bit(1)

CLK Polarity

Select Bit

Transfer Format

Select Bit(3)

Enabled when CRD=0

0 : Selects CTS function

1 : Selects RTS function

0 0: Selects f1

0 1: Selects f8

1 0: Selects f2n(2)

1 1: Do not set to this value

0 : Data in the transmit register

(during transmission)

1 : No data in the transmit register

(transmission is completed)

0 : Enables CTS/RTS function

1 : Disables CTS/RTS function

0 : TxDi/SDAi and SCLi are ports for the

CMOS output

1 : TxDi/SDAi and SCLi are ports for the

N-channel open drain output

0 : LSB first

1 : MSB first

Bit Name

Bit

Symbol

Function

NOTES:

1. P70/TxD2 and P71/SCL2 are ports for the N-channel open drain output, but not for the CMOS output.

2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

3. The UFORM bit setting is enabled when the SMD2 to SMD0 bits in the UiMR register are set to

"0012" (clock syncronous serial I/O mode) or "1012" (UART mode, 8-bit transfer data).

Set the UFORM bit to "1" when setting the SMD2 to SMD0 bits to"0102" (I2C mode), or to "0" when

setting them to "1002" (UART mode, 7-bit transfer data) or "1102" (UART mode, 9-bit transfer data).

0 : Data is transmitted on the falling edge

of the transfer clock and data is

received on the rising edge

1 : Data is transmitted on the rising edge of

the transfer clock and data is received

on the falling edge

Figure 17.4 U0C0 to U4C0 Registers

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