M32CSLASH86 datasheet(208/505 Pages) RENESAS

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Page 185

17. Serial I/O

)

(

UARTi Transmit Buffer Register (i=0 to 4)(1)

Symbol

Address

After Reset

U0TB to U2TB 036B16-036A16, 02EB16-02EA16, 033B16-033A16

Indeterminate

U3TB, U4TB

032B16-032A16, 02FB16-02FA16

Indeterminate

Transmit data (D7 to D0)

Nothing is assigned.

When write, set to "0".

When read, its content is indeterminate.

Transmit data (D8)

NOTES:

1. Use the MOV instruction to set the UiTB register.

(b15 - b9)

(b7 - b0)

(b8)

Function

b15

Bit

Symbol

UARTi Receive Buffer Register (i=0 to 4)

Bit Name

Bit

Symbol

Address

After Reset

U0RB to U2RB 036F16 - 036E16, 02EF16 - 02EE16, 033F16 - 033E16

Indeterminate

U3RB, U4RB

032F16 - 032E16, 02FF16 - 02FE16

Indeterminate

Received data (D7 to D0)

ABT

(b10 - b9)

(b7 - b0)

(b8)

OER

FER

SUM

PER

Function

Overrun Error Flag(2)

Arbitration Lost

Detect Flag(1)

Framing Error

Flag(2, 3)

Parity Error Flag(2, 3)

Error Sum Flag(2, 3)

Received data (D8)

0: Not detected (win)

1: Detected (lose)

0: No overrun error occurs

1: Overrun error occurs

0: No framing error occurs

1: Framing error occurs

0: No parity error occurs

1: Parity error occurs

0: No error occurs

1: Error occurs

NOTES:

1. The ABT bit can be set to "0" only.

2. When the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disable) or the RE bit in

the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0".

When all OER, FER and PER bits are set to "0", the SUM bit is set to "0".

Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register.

3. These error flags are disabled when the SMD2 to SMD0 bits are set to "0012" (clock synchronous serial

I/O mode) or to "0102" (I2C mode). When read, the contents are indeterminate.

b15

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Figure 17.2 U0TB to U4TB Registers and U0RB to U4RB Registers

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