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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M32C/86 데이터시트(PDF) 219 Page - Renesas Technology Corp |
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M32C/86 데이터시트(HTML) 219 Page - Renesas Technology Corp |
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219 / 505 page  Page 196 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (Clock Synchronous Serial I/O) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Tc TCLK Pulse stops because the TE bit is set to "0" Data is set in the UiTB register Transfer Clock TE bit in UiC1 register TI bit in UiC1 register CLKi TxDi TXEPT bit in UiC0 register "H" "L" CTSi IR bit in SiTIC register "0" "1" Pulse stops because an "H" signal is applied to CTSi Data is transferred from the UiTB register to the UARTi transmit register Set to "0" by an interrupt request acknowledgement or by program TC=TCLK=2(m+1)/fj fj : Count source frequency set in the UiBRG register (f1, f8, f2n(1)) m : Setting value of the UiBRG register i = 0 to 4 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division ( n=0) or divide-by-2n (n=1 to 15). The above applies to the following settings: • The CKDIR bit in the UiMR register is set to "0" (internal clock selected) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "0" (CTS function selected) • The CKPOL bit the in UiC0 register is set to "0" (data transmitted on the falling edge of the transfer clock) • The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register) (1) Transmit Timing (Internal clock selected) "0" "1" "0" "1" "0" "1" Dummy data is set in the UiTB register TE bit in UiC1 register TI bit in UiC1 register CLKi RxDi RI bit in UiC1 register RTSi RE bit in UiC1 register Data is transferred from the UiTB register to the UARTi transmit register Read by the UiRB register The above applies to the following settings: • The CKDIR bit in the UiMR register is set to "1" (external clock selected) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "1" (RTS function selected) • The CKPOL bit in the UiC0 register is set to "0" (Data is received on the rising edge of the transfer clock) IR bit in SiRIC register Set to "0" by an interrupt request acknowledgement or by program 1 / fEXT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 D7 D6 OER bit in UiRB register D6 Meet the following conditions while an "H" signal is applied to the CLKi pin before receiving data: • Set the TE bit in the UiC1 register to "1" (transmit enable) • Set the RE bit in the UiC1 register to "1" (receive enable) • Write dummy data to the UiTB register fEXT: External clock frequency i=0 to 4 (2) Receive Timing (External clock selected) "H" "L" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" An "L" signal is applied when the UiRB register is read Received data is taken in Date is transferred from the UARTi receive register to the UiRB register Figure 17.10 Transmit and Receive Operation |
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