M32CSLASH86 datasheet(223/505 Pages) RENESAS

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Page 200

17. Serial I/O (UART)

)

(

Table 17.7 lists register settings. Tables 17.8 to 17.10 list pin settings. When UARTi (i=0 to 4) operating

mode is selected, the TxDi pin outputs a high-level ("H") signal before transfer is started (the TxDi pin is in

a high-impedance state when the N-channel open drain output is selected). Figure 17.14 shows an ex-

ample of a transmit operation in UART mode. Figure 17.15 shows an example of a receive operation in

UART mode.

Table 17.7 Register Settings in UART Mode

Bit

Function

UiTB

8 to 0

Set transmit data(1)

UiRB

8 to 0

Received data can be read(1)

OER, FER,

Error flags

PER, SUM

UiBRG

7 to 0

Set bit rate

UiMR

SMD2 to SMD0

Set to "1002" when transfer data is 7 bits long

Set to "1012" when transfer data is 8 bits long

Set to "1102" when transfer data is 9 bits long

CKDIR

Select the internal clock or external clock

STPS

Select stop bit length

PRY, PRYE

Select parity enable or disable, odd or even

IOPOL

Select TxD and RxD I/O polarity

UiC0

CLK1, CLK0

Select count source for the UiBRG register

CRS

_______

Select either CTS or RTS when using either

TXEPT

Transfer register empty flag

CRD

________

_______

Select the CTS or RTS function enabled or disabled

NCH

Select output format of the TxDi pin

CKPOL

Set to "0"

UFORM

Select the LSB first or MSB first when a transfer data is 8 bits long

Set to "0" when transfer data is 7 bits or 9 bits long

UiC1

Set to "1" to enable data transmission

Transfer buffer empty flag

Set to "1" to enable data reception

Reception complete flag

UiIRS

Select what causes the UARTi transmit interrupt to be generated

UiRRM

Set to "0"

UiLCH

Select whether data logic is inversed or not inversed when a transfer data is

7 bits or 8 bits long. Set to "0" when transfer data is 9 bits long

UiERE

Set to either "0" or "1"

UiSMR

7 to 0

Set to "0016"

UiSMR2

7 to 0

Set to "0016"

UiSMR3

7 to 0

Set to "0016"

UiSMR4

7 to 0

Set to "0016"

NOTES:

1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long.

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