M32CSLASH86 datasheet(231/505 Pages) RENESAS

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Page 208

17. Serial I/O (Special Function)

)

(

Table 17.13 Register Settings in I2C Mode

Bit

Function

Master

Slave

UiTB

7 to 0

Set transmit data

UiRB

7 to 0

Received data can be read

ACK or NACK bit can be read

ABT

Arbitration lost detect flag

Disabled

OER

Overrun error flag

UiBRG

7 to 0

Set bit rate

Disabled

UiMR

SMD2 to SMD0

Set to "0102"

CKDIR

Set to "0"

Set to "1"

IOPOL

Set to "0"

UiC0

CLK1, CLK0

Select count source of the UiBRG register

Disabled

CRS

Disabled because the CRD bit is set to "1"

TXEPT

Transfer register empty flag

CRD, NCH

Set to "1"

CKPOL

Set to "0"

UFORM

Set to "1"

UiC1

Set to "1" to enable data transmission

Transfer buffer empty flag

Set to "1" to enable data reception

Reception complete flag

UiRRM, UiLCH,

Set to "0"

UiERE

UiSMR

IICM

Set to "1"

ABC

Select an arbitration lost detect timing

Disabled

BBS

Bus busy flag

7 to 3

Set to "000002"

UiSMR2

IICM2

See Table 17.14

CSC

Set to "1" to enable clock synchronization

Set to "0"

SWC

Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit

of the transfer clock

ALS

Set to "1" to terminate SDAi output when

Not used. Set to "0"

detecting the arbitration lost

STC

Not used. Set to "0"

Set to "1" to reset UARTi

by detecting the start condition

SWC2

Set to "1" for an "L" signal output from SCL forcibly

SDHI

Set to "1" to disable SDA output

SU1HIM

Set to "0"

UiSMR3

SSE

Set to "0"

CKPH

See Table 17.14

DINC, NODC, ERR Set to "0"

DL2 to DL0

Set digital delay value

UiSMR4

STAREQ

Set to "1" when generating a start condition

Not used. Set to "0"

RSTAREQ

Set to "1" when generating a restart condition

STPREQ

Set to "1" when generating a stop condition

STSPSEL

Set to "1" when using a condition generating function

ACKD

Select ACK or NACK

ACKC

Set to "1" for ACK data output

SCLHI

Set to "1" to enable SCL output stop when

Not used. Set to "0"

detecting stop condition

SWC9

Not used. Set to "0"

Set to "1" to fix an "L" signal output

from SCLi on the falling edge of the

ninth bit of the transfer clock

IFSR

IFSR6, IFSR7

Set to "1"

i=0 to 4

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