M32CSLASH86 datasheet(227/505 Pages) RENESAS

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17. Serial I/O (UART)

)

(

TxDi

(no inverse)

Transfer Clock

"H"

"L"

"H"

"L"

(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse)

TxDi

(inverse)

"H"

"L"

Transfer Clock

"H"

"L"

(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)

NOTES:

1. The above applies to when the UFORM bit in the UiC0 register is set to "0"

(LSB first), the STPS bit in the UiMR register is set to "0" (1 stop bit) and

the PRYE bit is set to "1" (parity enabled).

ST : Start bit

P : Parity bit

SP : Stop bit

ST : Start bit

P : Parity bit

SP : Stop bit

CLKi

TxDi

RxDi

(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)

(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)

CLKi

TxDi

RxDi

NOTES:

1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is

transmitted on the falling edge of the transfer clock and received on the rising edge)

and the UiLCH bit in the UiC1 register is set to "0" (no inverse).

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

17.2.2 Selecting LSB First or MSB First

As shown in Figure 17.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.

This function is available for 8-bit transfer data.

Figure 17.16 Transfer Format

17.2.3 Serial Data Logic Inverse

When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB

Figure 17.17 Serial Data Logic Inverse

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