M32CSLASH86 datasheet(238/505 Pages) RENESAS

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17. Serial I/O (Special Function)

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17.3.6 SDA Input

When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are

stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK.

When the IICM2 bit is set to "1", the first seven bits (D7 to D1) of received data are stored into bits 6 to 0

in the UiRB register. Store the eighth bit (D0) into bit 8 in the UiRB register.

If the IICM2 bit is set to "1" and the CKPH bit in the UiSMR3 register is set to "1", the same data as that of

when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising

edge of the ninth bit of the transfer clock.

17.3.7 ACK, NACK

When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the

ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin provides the value output

set in the ACKD bit in the UiSMR4 register.

If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H")

on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the

SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock.

When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection.

17.3.8 Transmit and Receive Reset

When the STC bit in the UiSMR2 register (i=0 to 4) is set to "1" (UARTi initialization enabled) and a start

condition is detected,

- the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift

unchanged between when the clock is applied and when the first bit data output is provided. The value

remains the same as when start condition was detected.

- the receive shift register is reset and the first bit start receiving when the next clock is applied.

- the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes "L" on the falling edge of the

ninth bit of the transfer clock.

If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains

unchanged. Select the external clock as the transfer clock when using this function.

M32C/86 데이터시트(PDF) 238 Page - Renesas Technology Corp