M32CSLASH86 datasheet(240/505 Pages) RENESAS

240 / 505 page

Page 217

17. Serial I/O (Special Function)

)

(

Table 17.20 Register Settings in Special Mode 2

Bit

Function

UiTB

7 to 0

Set transmit data

UiRB

7 to 0

Received data can be read

OER

Overrun error flag

UiBRG

7 to 0

Set bit rate

UiMR

SMD2 to SMD0

Set to "0012"

CKDIR

Set to "0" in master mode or "1" in slave mode

IOPOL

Set to "0"

UiC0

CLK1, CLK0

Select count source for the UiBRG register

CRS

Disabled because the CRD bit is set to "1"

TXEPT

Transfer register empty flag

CRD

Set to "1"

NCH

Select the output format of the TxDi pin

CKPOL

Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in

the UiSMR3 register

UFORM

Select either LSB first or MSB first

UiC1

Set to "1" to enable data transmission and reception

Transfer buffer empty flag

Set to "1" to enable data reception

Reception complete flag

UiIRS

Select what causes the UARTi transmit interrupt to be generated

UiRRM

Set to "1" to enable continuous receive mode

UiLCH, SCLKSTPB Set to "0"

UiSMR

7 to 0

Set to "0016"

UiSMR2

7 to 0

Set to "0016"

UiSMR3

SSE

Set to "1"

CKPH

Clock phase can be set by the combination of the CKPH bit and the CKPOL bit

in the UiC0 register

DINC

Set to "0" in master mode or "1" in slave mode

NODC

Set to "0"

ERR

Fault error flag

7 to 5

Set to "0002"

UiSMR4

7 to 0

Set to "0016"

i=0 to 4

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