M32CSLASH86 datasheet(257/505 Pages) RENESAS

257 / 505 page

Page 234

17. Serial I/O (Special Function)

)

(

Figure 17.30 SIM Interface Connection

17.7.1 Parity Error Signal

17.7.1.1 Parity Error Signal Output Function

When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1" (output), the parity error signal output

can be provided. The parity error signal output is provided when a parity error is detected upon

receiving data. A low-level ("L") signal output is provided from the TxDi pin in the timing shown in

Figure 17.31. When reading the UiRB register during a parity error output, the PER bit in the UiRB

neously.

17.7.1.2 Parity Error Signal

To determine whether the parity error signal is output, the port that shares a pin with the RxDi pin is

read by using an end-of-transmit interrupt routine.

Microcomputer

SIM card

TxDi

RxDi

i=0 to 4

Figure 17.31 Parity Error Signal Output Timing (LSB First)

Hi-Z

RxDi

TxDi

Recieve

Complete Flag

"H"

"L"

"H"

"L"

"1"

"0"

NOTES:

1. The above applies to direct format conditions.

(The PRY bit is set to "1", the UFORM bit is set to "0",

and the UiLCH bit is set to "0").

ST : Start bit

P : Even parity

SP : Stop bit

i=0 to 4

"H"

"L"

Transfer Clock

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