M32CSLASH86 datasheet(289/505 Pages) RENESAS

289 / 505 page

Page 266

22. Intelligent I/O

)

(

Figure 22.4 G1BCR1 Register

Base Timer Control Register 11

Symbol

Address

After Reset

G1BCR1

012316

X000 000X2

Bit Name

Function

Bit

Symbol

RST1

(b0)

(b3)

(b7)

RST2

Base Timer

Start Bit

BTS

UD0

UD1

Base Timer Reset

Cause Select Bit 1

Base Timer Reset

Cause Select Bit 2

Counter Increment/

Decrement Control Bit

0: Base timer is reset

1: Base timer starts counting

: Counter increment mode

: Counter increment/decrement mode

: Two-phase pulse signal processing

mode(3)

: Do not set to this value

Reserved Bit

Set to "0"

NOTES:

1. The base timer is reset after two fBT1 clock cycles when the base timer value matches the G1PO0

the G1POj register (j=1 to 7) for the waveform generating function and communication function must

be set to a value smaller than the G1PO0 register.

2. The IPSA_0 bit in the IPSA register can select the INT0 or INT1 pin.

3. In two-phase pulse signal processing mode, the base timer is not reset, even though the RST1 bit is

set to "1", if the counter is decremented after two clock cycles when the base timer value matches the

G1PO0 register setting.

0: The base timer is not reset by

matching with the G1PO0 register

1: The base timer is reset by matching

with the G1PO0 register(1)

0: The base timer is not reset by

applying "L" to the INT0 or INT1 pin

1: The base timer is reset by applying

"L" to the INT0 or INT1 pin(2)

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

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