SH7021 datasheet(78/509 Pages) RENESAS

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4.7

Stack Status after Exception Processing

Table 4.10 shows the stack after exception processing.

Table 4.10

Stack after Exception Processing

Type

Stack Status

Type

Stack Status

Address

error

Upper 16 bits

Lower 16 bits

Upper 16 bits

Lower 16 bits

Address of

instruction

after instruc-

tion that has

finished

executing

Interrupt

Upper 16 bits

Lower 16 bits

Upper 16 bits

Lower 16 bits

Address of

instruction

after instruc-

tion that

has finished

executing

Trap

instruc-

tion

Upper 16 bits

Lower 16 bits

Upper 16 bits

Lower 16 bits

Address of

instruction

after TRAPA

instruction

Illegal

slot

instruc-

tion

Upper 16 bits

Lower 16 bits

Upper 16 bits

Lower 16 bits

Branch

destination

address of

delayed

branch

instuction

General

illegal

instruc-

tion

Upper 16 bits

Lower 16 bits

Upper 16 bits

Lower 16 bits

Start add-

ress of

illegal

instruction

Note:

Stack status is based on a bus width of 16 bits.

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