| 전자부품 데이터시트 검색엔진 |
|
R8C16 데이터시트(PDF) 49 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R8C16 데이터시트(HTML) 49 Page - Renesas Technology Corp |
|
49 / 279 page ![]() R8C/16 Group, R8C/17 Group 7. Processor Mode Rev.2.10 Jan 19, 2006 Page 36 of 254 REJ09B0169-0210 Figure 7.2 PM1 Register Processor Mode Register 1 (1) Symbol Address After Reset PM1 0005h 00h Bit Symbol Bit Name Function RW NOTES : 1. 2. — Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. Set to “0” — (b0) Reserved Bit 0 — (b1) b7 b6 b5 b4 b3 b2 — b1 b0 0 0 : Watchdog Timer Interrupt 1 : Watchdog Timer Reset(2) RW RW — (b6-b3) PM12 WDT Interrupt/Reset Sw itch Bit The PM12 bit is set to “1” by a program (It remains unchanged even if it is set to “0”). When the CSPRO bit in the CSPR register is set to “1” (selects count source protect mode), the PM12 bit is automatically set to “1”. Reserved Bit Set to “0” Set the PRC1 bit in the PRCR register to “1” (w rite enable) before rew riting to this register. Nothing is assigned. When w rite, set to “0”. When read, its content is “0”. — (b7) RW |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |