R8C16 datasheet(71/279 Pages) RENESAS

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R8C/16 Group, R8C/17 Group

11. Interrupt

Rev.2.10

Jan 19, 2006

Page 58 of 254

REJ09B0169-0210

11.1.3

Special Interrupts

Special interrupts are non-maskable interrupts.

11.1.3.1

Watchdog Timer Interrupt

The watchdog timer interrupt is generated by the watchdog timer. Reset the watchdog timer after the

watchdog timer interrupt is generated. For details, refer to 12. Watchdog Timer.

11.1.3.2

Oscillation Stop Detection Interrupt

Oscillation Stop Detection Interrupt is generated by the oscillation stop detection function. For details

of the oscillation stop detection function, refer to 9. Clock Generation Circuit.

11.1.3.3

Voltage Monitor 2 Interrupt

The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage

detection circuit, refer to 6. Voltage Detection Circuit.

11.1.3.4

Single-Step Interrupt, Address Break Interrupt

Do not use the single-step interrupt. For development tools only.

11.1.3.5

Address Match Interrupt

The address match interrupt is generated immediately before executing an instruction that is stored

into an address indicated by the RMAD0 to RMAD1 registers when the AIER0 or AIER1 bit in the

AIER register which is set to "1" (address match interrupt enable). For details of the address match

interrupt, refer to 11.4 Address Match Interrupt.

11.1.4

Peripheral Function Interrupt

The peripheral function interrupt is generated by the internal peripheral function of the

microcomputer and a maskable interrupt. Refer to Table 11.2 Relocatable Vector Tables for the

interrupt factor of the peripheral function interrupt. For details of the peripheral function, refer to the

description of each peripheral function.

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