SH7713 datasheet(70/904 Pages) RENESAS

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Section 2 CPU

Rev.1.50 Aug. 30, 2006 Page 30 of 860

REJ09B0288-0150

Table 2.1

Logical Address Space

Address Range Name

Mode

Description

H'00000000 to

H'7FFFFFFF

P0/U0

Privileged/user mode

2-Gbyte physical space, cacheable, address

translatable

In user mode, only this address space can be

accessed.

H'80000000 to

H'9FFFFFFF

Privileged mode

0.5-Gbyte physical space, cacheable

H'A0000000 to

H'BFFFFFFF

Privileged mode

0.5-Gbyte physical space, non-cacheable

H'C0000000 to

H'DFFFFFFF

Privileged mode

0.5-Gbyte physical space, cacheable, address

translatable

H'E0000000 to

H'FFFFFFFF

Privileged mode

0.5-Gbyte control space, non-cacheable

2.2.2

External Memory Space

The LSI uses 29 bits of the 32-bit logical address to access external memory. In this case, 0.5-

Gbyte of external memory space can be accessed. The external memory space is managed in area

units. Different types of memory can be connected to each area, as shown in figure 2.2. For

details, please refer to section 12, Bus State Controller (BSC).

In addition, area 1 in the external memory space is used as an on-chip I/O space where most of

this LSI’s on-chip I/Os are mapped. *

Normally, the upper three bits of the 32-bit logical address are masked and the lower 29 bits are

used for external memory addresses.*

2 For example, address H'00000100 in the P0 area, address

H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3

area of the logical address space are mapped into address H’00000100 of area 0 in the external

memory space. The P4 area in the logical address space is not mapped into the external memory

address. If an address in the P4 area is accessed, an external memory cannot be accessed.

Notes: 1. To access an on-chip I/O mapped into area 1 in the external memory space, access the

address from the P2 area which is not cached in the logical address space.

2. If the address translation unit is enabled, arbitrary mapping in page units can be

specified. For details, refer to section 5, Memory Management Unit (MMU).

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