SH7713 datasheet(114/904 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 74 of 860

REJ09B0288-0150

3.2.3

CPU Register Sets

In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three

control registers: a repeat start register (SR), repeat end register (RE), and module register are

added as control registers.

16 15

28 27

9876543210

RC[11:0]

DSP DMY DMX M

RF1 RF0

Repeat Start register (RS)

Status Register

(SR)

Repeat End register (RE)

MODulo register (MOD)

Figure 3.2 CPU Registers in DSP Mode

Extension of Status Register (SR): In DSP mode, the following control bits are added to the

status register (SR). These added bits are called DSP extension bits. These DSP extension bits are

valid only in DSP mode.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 28



For details, refer to section 2, CPU.

27 to 16 RC11 to

RC0

All 0

R/W

Repeat Counter

Holds the number of repeat times in order to perform loop

control, and can be modified in privileged mode, privileged

DSP mode, or user DSP mode. At reset, this bit is initialized

to 0. This bit is not affected in the exception handling state.

15 to 13



For details, refer to section 2, CPU.

DSP

R/W

DSP Bit

Enables or disables the DSP extended functions. If this bit

is set to 1, the DSP extended functions are enabled. This bit

can be modified in privileged mode or privileged DSP mode.

This bit cannot be modified in user DSP mode. At reset, this

bit is initialized to 0. This bit is not affected in the exception

handling state.

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