SH7713 datasheet(158/904 Pages) RENESAS

158 / 904 page

Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 118 of 860

REJ09B0288-0150

3.5.4

ALU Fixed-Point Operations

Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type

of operation and table 3.22 shows the correspondence between each operand and registers.

Source 1

Destination

ALU

DSR

Source 2

Guard

V DC

Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow

Note:

The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the

base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit

parts when a register not providing the guard-bit parts is specified as the source operand.

When a register not providing the guard-bit parts is specified as a destination operand, the

lower 32 bits of the operation result are input into the destination register.

ALU fixed-point operations are executed between registers. Each source and destination operand

are selected independently from one of the DSP registers. When a register providing guard bits is

specified as an operand, the guard bits are activated for this type of operation. These operations

are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the

MA stage in which memory access is performed.

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