| 전자부품 데이터시트 검색엔진 |
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SH7721 데이터시트(PDF) 100 Page - Renesas Technology Corp |
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SH7721 데이터시트(HTML) 100 Page - Renesas Technology Corp |
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100 / 1524 page ![]() Section 2 CPU Rev. 3.00 Jan. 18, 2008 Page 38 of 1458 REJ09B0033-0300 2.1.2 Processing Modes This LSI supports two processing modes: user mode and privileged mode. These processing modes can be determined by the processing mode bit (MD) in the status register (SR). If the MD bit is cleared to 0, the user mode is selected. If the MD bit is set to 1, the privileged mode is selected. The CPU enters the privileged mode by a transition to reset state or exception handling state. In the privileged mode, any registers and resources in address spaces can be accessed. Clearing the MD bit in the SR to 0 puts the CPU in the user mode. In the user mode, some of the registers, including SR, and some of the address spaces cannot be accessed by the user program and system control instructions cannot be executed. This function effectively protects the system resources from the user program. To change the processing mode from user to privileged mode, a transition to exception handling state is required. Note: To call a service routine used in privileged mode from user mode, the LSI supports an unconditional trap instruction (TRAPA). When a transition from user mode to privileged mode occurs, the contents of the SR and PC are saved. A program execution in user mode can be resumed by restoring the contents of the SR and PC. To return from an exception processing program, the LSI supports an RTE instruction. (From any states) Power-on reset Manual reset Reset state Program execution state Low-power consumption state Exception handling state An exception is accepted Exception handling routine starts Reset processing routine starts An exception is accepted Multiple exceptions SLEEP instruction Figure 2.1 Processing State Transitions |
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