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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7721 데이터시트(PDF) 121 Page - Renesas Technology Corp |
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SH7721 데이터시트(HTML) 121 Page - Renesas Technology Corp |
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121 / 1524 page  Section 2 CPU Rev. 3.00 Jan. 18, 2008 Page 59 of 1458 REJ09B0033-0300 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. Immediate #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. Note: For addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x1, x2, or x4) according to the operand size to clarify the LSI operation. For details on assembler description, refer to the description rules in each assembler. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC relative with displacement disp:8, disp:12 ; PC relative |
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