SH7721 datasheet(155/1524 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev. 3.00 Jan. 18, 2008 Page 93 of 1458

REJ09B0033-0300

Table 3.4 shows the addresses to be specified in the repeat start register (RS) and repeat end

Table 3.4

RS and RE Setting Rule

Number of Instructions in Repeat Loop

≥4

RptStart0 + 8

RptStart0 + 6

RptStart0 + 4

RptStart

RptStart0 + 4

RptEnd3 + 4

Note:

The terms used above in table 3.2, are defined as follows.

RptStart: Address of the repeat start instruction

RptStart0: Address of the instruction one instruction prior to the repeat start instruction

RptEnd3: Address of the instruction three instructions prior to the repeat end instruction

(2)

Repeat Control Instructions and Repeat Control Macros

To describe a repeat loop, the RS and RE registers must be specified appropriately by the LDRS

and LDRS instructions and then the number of repetitions must be specified by the SERTC

instruction. An 8-bit immediate data or a general register can be used as an operand of the SETRC

instruction. To specify the RC as a value greater than 256, use SETRC Rm type instructions.

Table 3.5

Repeat Control Instructions

Instruction

Operation

Number of

Execution States

LDRS @(disp,PC)

Calculates (disp x 2 + PC) and stores the result to the

RS register

LDRE @(disp,PC)

Calculates (disp x 2 + PC) and stores the result to the

RE register

SETRC #imm

Sets 8-bit immediate data imm to the RC[11:0] bits of

the SR register and sets the information related to the

number of repetitions to the RF[1:0] bits of the SR.

RC[11:0] can be specified as 0 to 255.

SETRC Rm

Sets the[11:0] bits of the Rm register to the RC[11:0]

bits of the SR register and sets the information related

to the number of repetitions to the RF[1:0] bits of the

SR.

RC[11:0] can be specified as 0 to 4095.

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