7905 datasheet(91/565 Pages) RENESAS

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7905 Group User’s Manual Rev.1.0

INTERRUPTS

6-10

6.5 Interrupt priority level detection circuit

The interrupt priority level detection circuit is used to select the interrupt with the highest priority level from

multiple interrupt requests sampled at the same timing. Figure 6.5.1 shows the interrupt priority level detection

circuit.

6.5 Interrupt priority level detection circuit

Fig. 6.5.1 Interrupt priority level detection circuit

IPL

INT4

INT3

INT6

INT5

INT7

UART2 transmit

UART2 receive

INT2

INT1

INT0

Level 0 (Initial value)

Interrupt priority level

UART1 transmit

UART1 receive

UART0 transmit

UART0 receive

Timer B2

Timer B1

Timer B0

Timer A4

Timer A3

Timer A2

Timer A1

Timer A0

Processor interrupt priority level

Interrupt with the highest priority level

Interrupt disable flag (I)

Watchdog timer interrupt

Reset

Acceptance of interrupt request

Timer A9

Timer A8

Timer A7

Timer A6

Timer A5

A-D conversion

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