M38048FDHKP datasheet(230/387 Pages) RENESAS

230 / 387 page

2-106

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

➅ Generating of STOP condition

Confirm correct completion of communication at ➄ before generating the STOP condition. After

confirming correct completion, store the received data (upper data).

Clear the ACK bit (bit 6 of address 001516) to “0”, in which ACK is returned, and generate the

STOP condition. The communication mode is set to the slave receive mode by the occurrence of

STOP condition.

When the MST bit (bit 7 of address 001316) is “0”, return to the process ➀, because other devices

have priority to communicate.

Fig. 2.5.27 Generating of STOP condition

AL (address 001316), bit 3 ?

1 (detected)

0 (not detected)

S1 (address 001316)

← 110100002

End

Re-transmission preparation

Receive data buffer

← S0 (address 001116)

S2 (address 001516)

← 100001012

BB (address 001316), bit5 ? (Note)

0 (bus free)

1 (bus busy)

PIN (address 001316), bit 4 ?

1 (STOP condition)

0 (upper data transmitted)

Note: Use the branch bit instruction to check bus busy.

Also, execute the time out processing separately, if neccessary.

• Judgment of bus hold

• Judgment of arbitration lost detection

• Set “ACK is returned”

• Judgment of bus busy

• STOP condition occurrence

• Receive data read and save

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