M38048FDHKP datasheet(232/387 Pages) RENESAS

부품명	M38048FDHKP

상세설명	8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES

PDF	387 Pages

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제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

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232 / 387 page

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APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2004

REJ09B0212-0100Z

3804 Group (Spec.H)

➀ Reception of START condition; Transmission of ACK bit due to slave address correspondence

In the case of operation as the slave, all processes are performed in the interrupt after setting of

the slave reception in the main process, because an interrupt request does not occur until

correspondence of a slave address.

In the first interrupt, after confirming correspondence of the slave address, write dummy data to

receive a command into the I2C data shift register.

Fig. 2.5.29 Reception process of START condition and slave address

AAS (address 001316), bit 2 ?

1 (corresponded)

0 (not corresponded)

End

S0 (address 001116)

← 111111112

Error processing

PIN (address 001316), bit 4 ?

1 (STOP condition)

0 (slave address received)

S1 (address 001316)

← 000100002

• Judgment of bus hold

• Judgment of slave address correspondence

• Slave receive mode set

• Dummy data write to I2C data shift register

M38048FDHKP 데이터시트(PDF) 232 Page - Renesas Technology Corp