TDA9113

25/50

Horizontal and B+ Output Enable

0: Disabled, levels corresponding to “power

transistor off” on HOut and BOut pins (high

for HOut, high or low for BOut, depending

1: Enabled, horizontal deflection drive signal

on HOut pin providing that it is not inhibited

by another internal event (activated XRay

protection). B+ drive signal on BOut pin.

Programming the bit to 1 after prior value of 0,

will initiate soft start mechanism of horizontal

drive and of B+ DC/DC convertor if this is in ex-

ternal sawtooth configuration.

Selection of Edge of Horizontal drive signal to

phase B+ drive Output signal on BOut pin. Only

0: Falling edge

1: Rising edge

Test bits. They must be kept at 0 level by appli-

cation S/W.

Read-out flags

(52)

Flag indicating Detection of V synchronization

pulses on VSyn pin.

0: Not detected

1: Detected

Flag indicating Detection of H or HV synchroni-

sync pulses are detected, the flag is set and

latched. Disappearance of the sync signal will

not lead to reset of the flag.

0: Not detected

1: Detected.

Flag indicating Detection of Extracted Vertical

synchronization signal from composite H+V sig-

0: Not detected

1: Detected

Flag indicating Polarity of V synchronization

pulses applied on VSyn pin with respect to mean

level of the sync signal

0: Positive

1: Negative

Flag indicating Polarity of H or HV synchroniza-

to mean level of the sync signal

0: Positive

1: Negative

Alarm indicating that an event of excessive volt-

age has passed on XRay pin. Can only be reset

on reset.

0: No excess since last reset of the bit

1: At least one event of excess appeared

since the last reset of the bit, HOut inhibited

Status of “Locking” or stabilization of Vertical os-

cillator amplitude to an internal reference by

AGC regulation loop.

0: Locked (amplitude stabilized)

1: Not locked (amplitude non-stabilized)

Status of Locking of Horizontal PLL1

0: Locked

1: Not locked

Note 52: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last

reset (by means of the

that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided

between reset of the flag through

out of status register.