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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADV3201ASWZ 데이터시트(PDF) 11 Page - Analog Devices |
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ADV3201ASWZ 데이터시트(HTML) 11 Page - Analog Devices |
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11 / 36 page  ADV3200/ADV3201 Rev. 0 | Page 11 of 36 TRUTH TABLE AND LOGIC DIAGRAM Table 8. Operation Truth Table CS UPDATE CLK DATA IN DATA OUT RESET Operation/Comment X1 X X X X 0 Asynchronous reset. All outputs are disabled. The 193-bit shift register is reset to all 0s. 0 1 Datai2 Datai-193 1 The data on the serial DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 193 clock cycles later. 0 0 X X X 1 Switch matrix update. Data in the 193-bit shift register is trans- ferred into the parallel latches that control the switch array and sync-tip clamps. 1 X X X X 1 Chip is not selected. No change in logic. 1 X = don’t care. 2 Datai: serial data. OUT00 0 LSB 192 LE D CLR Q OUT00 1 LSB 191 LE D CLR Q OUT00 2 LSB 190 LE D CLR Q OUT00 3 LSB 189 LE D CLR Q OUT00 4 LSB 188 LE D CLR Q OUT00 EN MSB 187 LE D CLR Q OUT01 0 LSB 186 LE D CLR Q OUT30 EN MSB 7 LE D CLR Q OUT31 0 LSB 6 LE D CLR Q OUT31 1 LSB 5 LE D CLR Q OUT31 2 LSB 4 LE D CLR Q OUT31 3 LSB 3 LE D CLR Q OUT31 4 LSB 2 LE D CLR Q OUT31 EN MSB 1 LE D CLR Q OUT31 SYNC TIP EN 0 LE D CLR Q D CLR Q CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK . . . DATA OUT DATA IN RESET RESET CLK CS UPDATE . . . DECODE SWITCH MATRIX 1024 32 OUTPUT ENABLE CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR Figure 6. Logic Diagram |
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