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ADV3201ASWZ 데이터시트(PDF) 12 Page - Analog Devices |
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ADV3201ASWZ 데이터시트(HTML) 12 Page - Analog Devices |
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12 / 36 page ![]() ADV3200/ADV3201 Rev. 0 | Page 12 of 36 I/O SCHEMATICS OUT VREF 4kΩ (ADV3201 ONLY) Figure 7. Enabled Output (See Also Figure 16) 3.7pF 4kΩ (ADV3201 ONLY) VREF OUT Figure 8. Disabled Output (See Also Figure 16) VNEG IN Figure 9. Receiver (See Also Figure 16) VNEG IN 5µA Figure 10. Receiver with Sync-Tip Clamp Enabled (See Also Figure 16) RESET DGND DVCC 1kΩ 25kΩ Figure 11. Reset Input (See Also Figure 16) DGND 1kΩ DGND 25kΩ (CS ONLY) CLK, UPDATE, DATA IN, OSDS, CS Figure 12. Logic Input (See Also Figure 16) DVCC DGND DATA OUT Figure 13. Logic Output (See Also Figure 16) VNEG VREF VCLAMP 50µA 6kΩ Figure 14. VCLAMP Input (See Also Figure 16) VNEG VPOS VPOS VREF 2.5kΩ (5kΩ FOR ADV3201) 2.5kΩ (5kΩ FOR ADV3201) Figure 15. VREF Input (See Also Figure 16) VPOS VNEG VREF, VCLAMP, OSD, IN, OUT DVCC DGND CLK, RESET, UPDATE, CS, DATA IN, DATA OUT, OSDS Figure 16. ESD Protection Map |
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