ADV3202/ADV3203

Rev. 0 | Page 10 of 20

TRUTH TABLE AND LOGIC DIAGRAM

Table 8. Operation Truth Table

CS

UPDATE

CLK

DATA INPUT

DATA OUTPUT

RESET

Operation/Comment

X

X

X

X

X

0

Asynchronous reset. All outputs are disabled; the 193-bit shift

register is reset to all 0s.

0

1

Datai1

1

The data on the serial DATA IN line is loaded into the serial

register. The first bit clocked into the serial register appears at

DATA OUT 193 clock cycles later.

0

0

X

X

X

1

Switch matrix update. Data in the 193-bit shift register transfers

into the parallel latches that control the switch array and sync-

tip clamps.

1

X

X

X

X

1

Chip is not selected. No change in logic.