MPC8640DEC datasheet(57/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

12 I2C

This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8640.

12.1

I2C DC Electrical Characteristics

Table 44 provides the DC electrical characteristics for the I2C interfaces.

12.2

I2C AC Electrical Specifications

Table 45 provides the AC timing parameters for the I2C interfaces.

Table 44. I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

VIH

0.7

× OVDD

OVDD +0.3

Input low voltage level

VIL

–0.3

0.3

× OVDD

Low level output voltage

VOL

00.2

× OVDD

Pulse width of spikes which must be suppressed

by the input filter

tI2KHKL

050

Input current each I/O pin (input voltage is

between 0.1

× OVDD and 0.9 × OVDD(max)

–10

μA3

Capacitance for each I/O pin

—10

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the

MPC8641 Integrated Host Processor Reference Manual for information on the digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

Table 45. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 44).

Parameter

Symbol 1

Min

Max

Unit

SCL clock frequency

fI2C

0400

kHz

Low period of the SCL clock

tI2CL

1.3

—

μs

High period of the SCL clock

tI2CH

0.6

—

μs

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs

Hold time (repeated) START condition (after this period,

the first clock pulse is generated)

tI2SXKL

0.6

—

μs

Data setup time

tI2DVKH

100

—

Data input hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0 2

—

μs

Rise time of both SDA and SCL signals

tI2CR

20 + 0.1 CB

300

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