MPC8640DEC datasheet(112/140 Pages) FREESCALE

112 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

112

Freescale Semiconductor

Thermal

platform. See note regarding cfg_platform_freq in Section 17, “Signal Listings” since it is a reset

configuration pin that is related to platform frequency.

18.4.2

Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed.

For FIFO GMII mode:

FIFO TX/RX clock frequency <= platform clock frequency / 4.2

For example, if the platform frequency is 500 MHz, the FIFO TX/RX clock frequency should be no more

than 119 MHz

For FIFO encoded mode:

FIFO TX/RX clock frequency <= platform clock frequency / 3.2

For example, if the platform frequency is 500 MHz, the FIFO TX/RX clock frequency should be no more

than 156 MHz

19 Thermal

This section describes the thermal specifications of the MPC8640.

19.1

Thermal Characteristics

Table 70 provides the package thermal characteristics for the MPC8640.

Table 69. Frequency Options of SYSCLK with Respect to Platform/MPX Clock Speed

MPX to

SYSCLK

Ratio

SYSCLK (MHz)

100

133

167

Platform/MPX Frequency (MHz) 1

SYSCLK frequency range is 66-167 MHz. Platform clock/ MPX

frequency range is 400 MHz, 500-533 MHz.

400

500

400

533

500

400

500

533

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