MPC8313CVRGDFB datasheet(17/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

DDR and DDR2 SDRAM

Figure 4 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.

Figure 4. DDR Input Timing Diagram

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Rev. 1.0 Silicon

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[

n] cycle time, MCK[n]/MCK[n] crossing

tMCK

610

ADDR/CMD output setup with respect to MCK

tDDKHAS

333 MHz

2.1

—

266 MHz

2.5

—

ADDR/CMD output hold with respect to MCK

tDDKHAX

333 MHz

2.4

—

266 MHz

3.15

—

MCS[

n] output setup with respect to MCK

tDDKHCS

333 MHz

2.4

—

266 MHz

3.15

—

MCS[

n] output hold with respect to MCK

tDDKHCX

333 MHz

2.4

—

266 MHz

3.15

—

MCK to MDQS Skew

tDDKHMH

–0.6

0.6

MDQ//MDM output setup with respect to

MDQS

tDDKHDS,

tDDKLDS

333 MHz

800

—

266 MHz

900

—

MDQ//MDM output hold with respect to MDQS

tDDKHDX,

tDDKLDX

333 MHz

900

—

266 MHz

1100

—

MDQS preamble start

tDDKHMP

–0.5

× tMCK – 0.6

–0.5

× tMCK + 0.6

MCK[

tMCK

MDQ[

MDQS[

tDISKEW

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