PCK953_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 9 October 2008

2 of 15

NXP Semiconductors

PCK953

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver

3.

Ordering information

Also refer to Table 8 “Packing information”.

4.

Functional diagram

5.

Pinning information

5.1 Pinning

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCK953BD

LQFP32

plastic low profile quad flat package; 32 leads; body 7

× 7 × 1.4 mm

SOT358-1

PCK953BD/G

Fig 1.

Functional diagram

PECL_CLK

002aae138

PECL_CLK

FB_CLK

PHASE

DETECTOR

VCO_SEL

BYPASS

MR/OE

PLL_EN

LPF

VCO

200 MHz

to 500 MHz

÷ 2

÷ 4

QFB

Q0 to Q6

Q7

7

Fig 2.

Pin configuration for LQFP32

PCK953BD

PCK953BD/G

Q1

FB_CLK

n.c.

Q2

n.c.

GNDO

n.c.

Q3

n.c.

GNDI

Q4

PECL_CLK

GNDO

002aae137

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17