PCK953BDSLASHG datasheet(4/15 Pages) NXP

4 / 15 page

PCK953_5

Product data sheet

Rev. 05 — 9 October 2008

4 of 15

NXP Semiconductors

PCK953

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver

Limiting values

Static characteristics

[1]

Vcm is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is

within the Vcm range and the input swing lies within the Vi(p-p) speciﬁcation.

[2]

The PCK953 outputs can drive series or parallel terminated 50

Ω (or 50 Ω to 0.5V

CC) transmission lines on the incident edge (see

Section 11 “Application information”).

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

−0.3

+4.6

input voltage

−0.3

VDD + 0.3

input current

±20

Tstg

storage temperature

−40

+125

°C

Table 5.

Static characteristics

Tamb =0 °C to 70 °C; VCC = 3.3 V ± 5 %, unless speciﬁed otherwise.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIH

HIGH-level input voltage

LVCMOS inputs

2.0

3.6

VIL

LOW-level input voltage

LVCMOS inputs

0.8

Vi(p-p)

peak-to-peak input voltage

PECL_CLK

300

1000

Vcm

common-mode voltage

PECL_CLK

[1] VCC − 1.5

VCC − 0.6

VOH

HIGH-level output voltage

IOH = −20 mA

[2] 2.4

VOL

LOW-level output voltage

IOL =20mA

[2] -

0.5

input current

±75

µA

input capacitance

CPD

power dissipation capacitance

per output

ICC

maximum quiescent supply current

all VCC pins

ICCPLL

maximum PLL supply current

VCCA pin only

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