CS5378 datasheet(16/88 Pages) CIRRUS

16 / 88 page

CS5378

DS639F2

SWITCHING CHARACTERISTICS

CLK, SYNC, MCLK, MSYNC, and MDATA

Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled.

4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

(Note 3)

CLK

32.768

MHz

Master Clock Duty Cycle

DTY

Master Clock Rise Time

tRISE

Master Clock Fall Time

tFALL

Master Clock Jitter

JTR

300

Synchronization after SYNC rising

(Note 4)

SYNC

-2

µs

MSYNC Setup Time to MCLK rising

tmss

MCLK rising to Valid MDATA

tmdv

MSYNC falling to MCLK rising

tmsf

MSYNC

MCLK

MDATA

Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing

tmsd

tmsh

Data1

Data2

SYNC

fMCLK

2.048 MHz

1.024 MHz

tmsd = TMCLK / 4

tmsd = 122 ns

tmsd = 244 ns

tmsh = TMCLK

tmsh = 488 ns

tmsh = 976 ns

Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.

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